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Senior Analog Layout Design Engineer

Job Title: Senior Analog Layout Design Engineer
Contract Type: Contract
Location: Cambridge, Cambridgeshire
Industry:
Salary: Negotiable
Start Date: asap
Duration: 3 Months
REF: KGANALOGENG_1505723739
Contact Name: Kerrie Gaurd
Contact Email: kerrie.gaurd@projectpeople.com
Job Published: 28 days ago

Job Description

Job Responsibilities

  • Responsible for layout design of a complex high-speed, low-noise mixed-signal IP in 16nm CMOS process
  • Hands-on block-level layout design and verification work, top-level IP floor-planning and integration, IC sign-off and tape-out
  • Work closely with analogue design team on IP floor-planning, trial layout design and parasitic extraction of critical structures. Propose circuit design changes
  • Co-ordinate layout design activities across multiple sites. Delegate block-level layout work when feasible
  • Collaborate with CAD, process technology, package design and digital back-end teams
  • Document own work and participate in design reviews
  • Provide guidance to junior team members

Skill and competencies

  • Experience in design of high-speed or RF layout in advanced CMOS processes.
  • 16nm FinFET experience an advantage.
  • High-speed ADC layout design experience an advantage.
    • Good understanding of high-speed and low-noise layout design techniques and requirements.
    • Experience in top-level integration and tape-outs.
    • Knowledge of semiconductor device physics and process technology.
    • Communicating effectively with circuit and layout designers.
  • Ability to work effectively and efficiently in a team environment

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