- Working in the device chipset team, Implementation of robust security IPs for integration on a variety of consumer devices, integration or design of third party security IPs on a variety of consumer devices and hardware test verification for different CAS/DRM use cases.
- Strong experience in security ASIC block design
- Experience in ASIC RTL level coding/verification (Verilog/System Verilog/UVM)
- Experience of System C modelling
- Experience with Test bench, Simulation, Formal Verification etc.
- Experience with Synthesis and Timing Analysis
- Experience with using scripting languages (makefiles/perl/python)
- Knowledge of Cadence and Synopsys EDA tools
- Excellent verbal and written communication skills.
- Knowledge of security blocks e.g. Security Processor, Cipher, Key ladder, RSA, Hash, Descrambler, TRNG, ARM Trustzone etc.
- Exposure to latest or emerging global CA subsystem requirements.
- Exposure to Protection of Assets e.g. Device Secrets, Content; General Attack vectors e.g. Extraction, Modification and Rollback of assets, Side Channel Attacks, DPA attacks, Device re-purposing and cloning, Fault Injection etc.
- Exposure to External lab certification procedures.
- Knowledge of RISC based CPU architecture and design, especially RISC-V
- Knowledge of spoken and/or written Mandarin.
- Electronics related bachelor degree or above
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