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SOC Design Engineer

Job Title: SOC Design Engineer
Contract Type: Permanent
Location: Bristol, England
Salary: Negotiable
Start Date: ASAP
REF: AT - SE_1520960787
Contact Name: Adam Thompson
Contact Email:
Job Published: 5 days ago

Job Description

SOC Design Engineer

A subsidiary of my client, a leading provider of ICT Solutions, is building world class security capability in Bristol, working with teams and partners internationally to drive the Security Architecture for their Consumer devices. You would be part of the team that will define and prove the robustness and security capability of the next generation of Set Top Boxes, Digital Televisions, IP Cameras and so on.

With the growth of IoT, the Bristol based security group will also be key in solving the critical issues around secure upgrade, privacy and trust of this emerging technology.


  • Implementation of robust security IPs for integration on a variety of Consumer devices
  • Integration or design of Third party security IPs on a variety of Consumer devices
  • Hardware test verification for different CAS/DRM use cases.



  • 4+ years' experience in security ASIC block design
  • Experience in ASIC RTL level coding/verification (Verilog/System Verilog/UVM)
  • Experience of System C modelling
  • Experience with Test bench, Simulation, Formal Verification etc.
  • Experience with Synthesis and Timing Analysis
  • Experience with using scripting languages (makefiles/perl/python)
  • Knowledge of Cadence and Synopsys EDA tools
  • Excellent verbal and written communication skills.


  • Knowledge of security blocks e.g. Security Processor, Cipher, Key ladder, RSA, Hash, Descrambler, TRNG, ARM Trustzone etc.
  • Exposure to latest or emerging global CA subsystem requirements.
  • Exposure to Protection of Assets e.g. Device Secrets, Content; General Attack vectors e.g. Extraction, Modification and Rollback of assets, Side Channel Attacks, DPA attacks, Device re-purposing and cloning, Fault Injection etc.
  • Exposure to External lab certification procedures.
  • Knowledge of RISC based CPU architecture and design, especially RISC-V

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