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Senior Analog Layout Design Engineer

Job Title: Senior Analog Layout Design Engineer
Contract Type: Contract
Location: Cambridge, Cambridgeshire
Salary: Negotiable
Start Date: ASAP
REF: NC2018030502_1522150491
Contact Name: Nick Chen
Contact Email:
Job Published: 12 months ago

Job Description

Senior Analog Layout Design Engineer

  • Salary dependent upon experience
  • Based in Cambridge, UK

Our client is a leading global information and communications technology (ICT) solutions provider. Through their dedication to customer-centric innovation and strong partnerships, they have established end-to-end advantages in telecom networks, devices and cloud computing. Their products and solutions have been deployed in over 140 countries, serving more than one third of the world's population.

Become a member of a world-class Analog design team in providing high performance Analog and mixed mode circuits for leading data communications and networking products. Designers have opportunities to design high performance Analog circuits. Team members participate in circuit architecture, circuit implementation, design review, layout, and silicon validation.


  • Responsible for layout design of a complex high-speed, low-noise mixed-signal IP in 16nm CMOS process
  • Hands-on block-level layout design and verification work, top-level IP floor-planning and integration, IC sign-off and tape-out
  • Work closely with analogue design team on IP floor-planning, trial layout design and parasitic extraction of critical structures. Propose circuit design changes
  • Co-ordinate layout design activities across multiple sites. Delegate block-level layout work when feasible
  • Collaborate with CAD, process technology, package design and digital back-end teams
  • Document own work and participate in design reviews
  • Provide guidance to junior team members


  • Experience in design of high-speed or RFlayoutinadvancedCMOS processes.
      • 16nm FinFET experience an advantage.
      • High-speed ADC layout design experience an advantage.
  • Good understanding of high-speed and low-noise layout design techniques and requirements.
  • Experience in top-level integration and tape-outs.
  • Knowledge of semiconductor device physics and process technology.
  • Communicating effectively with circuit and layout designers.
  • Ability to work effectively and efficiently in a team environment
  • Strong organisational and planning skills.
  • Excellent multi-tasking and prioritization skills.
  • Degree educated highly desirable.

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