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Senior Analog Layout Design Engineer

Job Title: Senior Analog Layout Design Engineer
Contract Type: Contract
Location: Cambridge, Cambridgeshire
Salary: Negotiable
Start Date: ASAP
REF: PP/C/SALDE/RW_1515435793
Contact Name: Rassin Wurie
Contact Email:
Job Published: about 1 year ago

Job Description

Senior Analog Layout Design Engineer



About The Company

My client, based in the Cambridgeshire area, are one of the leading network, telecommunications and mobile technology companies in the world. They are looking for a Senior Analog Layout Design Engineer.

About The Role

This role will be reporting into the R&D Manager - UK. You will be joining the Design Team to provide performance analog and mixed mode circuits for leading data communications and networking products, having the opportunity to design high performance analog circuits. Working together with the team, you will participate in developing circuit architecture, circuit implementation, design reviews, layouts and silicon validation.

You will work closely with analogue design team on IP floor-planning, trial layout design and parasitic extraction of critical structures to propose circuit design changes and collaborate with CAD, process technology, package design and digital back-end teams.

Main Responsibilities:

  • Layout design of a complex high-speed, low-noise mixed-signal IP in 16nm CMOS process.
  • Hands-on block-level layout design and verification work, top-level IP floor-planning and integration, IC sign-off and tape-out.
  • Co-ordinate layout design activities across multiple sites.
  • Delegate block-level layout work when feasible.
  • Document own work and participate in design reviews.
  • Provide guidance to junior team members.

About The Person

Skills & Experience Required:

  • Experience in designing high-speed or RF layout in advanced CMOS processes such as:
  • 16nm FinFET experience an advantage.
  • High-speed ADC layout design experience an advantage.
  • Good understanding of high-speed and low-noise layout design techniques and requirements.
  • Experience in top-level integration and tape-outs.
  • Knowledge of semiconductor device physics and process technology.
  • Communicating effectively with circuit and layout designers.
  • Ability to work effectively and efficiently in a team environment

If you are interested in this opportunity then please apply and I will aim to get back with 48 hours. Alternatively, you can contact me directly on

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